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In this project I actively worked either at the algo & specification phase or at HDL and SW development. The hardware used were the boards from VMETRO.
One of the main challenges was to align four A/D converters of 3Gsps. O Development of a latest generation Digital Receiver Unit. Finally, the block converts the estimations from the local antenna-panel reference, into a fixed reference, knowing the navigation data. The developed block estimates azimuth and elevation of the Direction of Arrival of an emission using the measures of phase difference among different channels, provided from a digital receiver. O Algorithmic study and implementation on FPGA, of a firmware aimed to phase goniometry. Purpose was to analyze captured images in order to extract emitting sources § Algo level SW for the Image Processing. SW has been developed partially under Visual Studio partially under WindRiver-workbench environment. § SW for the management of communication, and of MMI interface.
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§ HW COTS: Matrox Card for the acquisition and the processing of images, Power PC & VxWorks Curtiss-Wright, Host PC, HW for MIL-BUS-1553 management
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O Design of a simulator of Missile Warning System made of: O Design at system level and leading developement of the SW for management and allocation of HW resources for a Laser DIRCM system (Direct Infrared Counter Measures)
An important aspect of this project is the development of an engagement simulator (missile-target) to verify effectiveness of codes. O Leading an italian founded project for the study and developement of Jamming Codes (special modulations for the deceive of infrared missiles). Market of operation: Systems for Radar Electronic Warfare Qualification: System Architect / Analyst and Digital Designer O Development of a Simulink model for the simulation of the complete physical Layer of GSM communication systemĪpril 2005-June 2012: Elettronica SPA, ROMA § Antenna and Transceiver are COTS modules § Local Oscillator / synthesizer developments
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§ Software and FPGA/FW developments (VHDL, System Generator, C Language) Main sub-activities were ( all internal developments): O Leading the development of an FMCW Radar Sensor. Main project involving the area is the development of a low cost and reduced dimensions Radar Sensor and UAV SAR emulator. During first year of activities the area grew-up fastly and now reached an number of five engineers. O Built-up of Electronic HW/System Department. The system has been developed for an important non European global player of defense industry. The system is COTS based (Curtiss-Writght and 4DSP) and its purpose is to generate level) the echos as would been received by a SAR Radar Processor (targeted for UAV SAR) in order to test it in laboratory. O Leading the development of a Real Time SarRadar Emulator tailored for an UAV paltform. Qualification: Head of Electronic Developments Area Ø Currently leading the activities of a group made by myself and four other engineers Ø Model of proportional navigation based systems Ø Knowledge of C language and of the VxWorks environment for the implementation of SW functions for embedded systems Ø Knowledge of all the design flow for producing programming files for the FPGA starting from RTL-HDL description
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Ø Strong knowledge of VHDL language and of Xilinx System Generator Tool for the design of logic circuits and communication interface (PCI, VME, RocketIO, HotLink) (>7 y) Ø Architecture definition of electronic systems and Hardware/software partitioning Ø Capability to develop under Simulink environment simulation models for complex systems and functions Ø Knowledge of System Simulation/Signal Processing techniques and Matlab Language (> 5y) Ø Strong knowledge of Radar Systems and communication systems (GSM UMTS)